1. Field of Invention
This invention relates generally to semiconductor memories and specifically to a sense amplifier for sensing a bit line voltage of a semiconductor memory.
2. Description of Related Art
Sense amplifiers determine the binary state of a selected cell of a memory array by comparing the voltage on a selected bit line of the memory array to a reference voltage. For instance, FIG. 1 shows a EEPROM-type memory 10 including a cell array 12, a column decoder 14, sense amplifiers (SA) 16, and a reference circuit 18. The cell array 12 includes a plurality of NMOS non-volatile memory cells (not shown) arranged in sixteen columns, where the respective drains of the cells in a common column are connected to an associated bit line BL. Although not shown in FIG. 1 for simplicity, the memory 10 includes additional logic circuits such as, for instance, row decoders, input and output buffers, and so on.
As shown in FIG. 1, the sixteen bit lines BL of the array 12 are coupled to respective input terminals of the column decoder 14. The column decoder 14 includes four output terminals, each of which is associated with a specific group of four bit lines BL and connected to an associated sense amplifier 16 via an input/output (I/O) line. The reference circuit 18 includes a reference array (not shown for simplicity) having a configuration similar to that of the array 12, i.e., the reference array includes a plurality of NMOS memory cells similar to the NMOS memory cells of the array 12. Each sense amplifier 16 has an output terminal OUT, thereby providing the memory 10 with a four-bit output.
During read operations, four externally generated addresses are latched into the memory 10. These addresses are separated into row addresses and column address, where the row addresses are provided to four row decoders (not shown) and the column addresses are provided to the column decoder 14. In response to the row addresses, the row decoders select four respective rows of cells in the array 12. In response to the column address, the column decoder 14 selects four of the bit lines BL to couple to the four respective I/O lines. Signals indicative of the respective binary states of the four selected cells are provided to the four sense amplifiers 16. Each sense amplifier 16 compares the signal on its respective I/O line to a reference voltage V.sub.REF generated by the reference circuit 18 and, in response thereto, provides a signal indicative of the binary state of a corresponding cell of the array 12 onto its output terminal OUT. In this manner, four cells of the array 12 are read during each reading operation.
As mentioned above, the reference circuit 18 includes a reference array similar to, albeit smaller than, the array 12. In this manner, process variations arising during fabrication of the array 12 are matched in the reference array so that V.sub.REF tracks the bit line voltage. Typically, the reference voltage V.sub.REF is set at a predetermined value which approximates the bit line voltage. However, since this predetermined value is only an approximation, in actual applications the voltage differential between V.sub.REF and the bit line voltage may undesirably limit read speeds.